Explore Exciting Job Opportunities at IBM: Memory Layout Engineer in Bangalore
Are you ready to join a dynamic and innovative team at IBM's India Systems Development Lab (ISDL)? IBM is looking for talented Memory Layout Engineers in Bangalore to contribute to their cutting-edge technology projects. If you're passionate about VLSI design and want to work with industry leaders, this opportunity is for you. Read on to learn more about this exciting role and how you can be part of IBM's pioneering journey.
Memory Layout Engineer
Location: Bangalore, IN
Job Function: Infrastructure & Technology Professional
Introduction
India Systems Development Lab (ISDL) is a crucial part of IBM Systems' worldwide technology development efforts. Established in 1996, the Lab is headquartered in Bengaluru, India's Silicon Valley and startup hub, with strong presences in Pune and Hyderabad. The ISDL team delivers technology innovations across the entire IBM Systems portfolio, including z Systems, Power/OpenPOWER Systems, and Storage. The lab works across the entire stack, from processor design and firmware to operating systems and software-defined storage. To date, ISDL has contributed over 400+ patents in cutting-edge technologies and inventions.
Your Role and Responsibilities
In this role, you will design and layout complex VLSI (very large scale integration) circuits using graphic editing tools in cutting-edge technological nodes. You will be responsible for creating new physical design data from concepts, partial schematics, or a working knowledge of overall requirements. Key responsibilities include:
- Design Integrity: Check the design's integrity with respect to semiconductor ground rules and the logical function of the circuit.
- Physical Design: Convert symbolic circuit data (schematics) to physical shapes representing the semiconductor process.
- Team Coordination: Collaborate with extended teams and create methodologies.
- Problem Solving: Recognize complex problems, analyze situations, and implement solutions or develop new system elements, procedures, or processes.
- Leadership: Provide ongoing technical/operational guidance, conduct special projects, and manage departments.
Required Technical and Professional Expertise
- Experience: 8+ years in Memory Layout design for blocks like Caches, CAMs, Register files, multiport register files, compilers, etc.
- Hands-On Skills: Ability to work hands-on with memory IPs and innovate new ways of layout designing.
- Communication: Excellent communication skills for cross-site collaboration.
- Technical Knowledge: Understanding of various memory architectures, bit cells layouts, compiler layout design, and experience in technology nodes below 7nm.
- Design Skills: Proficiency in LVS, DRC, Antenna, DFM, EM, IR, and methodology check debugging and fixing.
- Leadership: Ability to drive collaborative initiatives with cross teams and possess a growth mindset.
- SRAM Designing: Experience in SRAM designing and scripting skills in PERL, Python, SKILL, and/or TCL is an added advantage.
Preferred Technical and Professional Expertise
- Automation Skills: Proficiency in PERL, Python, SKILL, and/or TCL.